Invited keynote
Striving at pushing the applications scalability to the limits, the DEEP project proposed an alternative heterogeneous HPC architecture: It matches the different concurrency levels existing in large and complex simulation codes into the hardware. In this architecture, a standard HPC cluster is connected to the so-called “Booster”: a cluster of autonomous accelerators. While the highly scalable parts of the application codes run on the energy efficient Booster, their low/medium scalable parts profit from the high single-thread performance of the Cluster side of the system.
Extending this concept, the DEEP-ER project adds to the Cluster-Booster architecture a multi-level memory hierarchy exploiting non-volatile memory technologies, with the ultimate goal of improving the I/O and resiliency capabilities of the system to better support data intensive applications.
Additional to their hardware developments culminating in various prototype systems, both the DEEP and DEEP‑ER projects have developed innovative software packages to support the newly introduced architecture, and extended existing programming environments preparing them for future heterogeneous Exascale systems.
This keynote will highlight some of the hardware and software technologies emerging from the European Exascale projects DEEP and DEEP-ER.
