Talk Title: Heterogeneous Computing

Rafael Asenjo received his B.S. and M.S. degrees in Telecommunications Engineering in 1993 and his Ph.D. degree in 1997, both from the University of Malaga, Spain. He has been an Associate Professor at the Dept. of Computer Architecture, Univ. Malaga, Spain, since 2001, where he leads a research group working on “productivity” in the context of high performance computing.  He collaborated on the IBM XL-UPC compiler and on the Cray’s Chapel runtime. In the last five years he has focused on productively exploiting heterogeneous chips. In 2013 and 2014 he visited UIUC to work on CPU+GPU chips. In 2015 and 2016 he also started to work on CPU+FPGA chips while visiting U. of Bristol. He served as General Chair of ACM PPoPP’16 and has also served as Program Committee member for PACT’17, EuroPar’17 and SC’15. His research interests include  heterogeneous programming models and architectures, parallelization of irregular codes, energy consumption and parallelizing compilers.